View W3EG264M72EFSUXXXD4_652864.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

White Electronic Designs
W3EG264M72EFSUXXXD4
ADVANCED*
1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA
FEATURES
Fast data transfer rate: PC-2100, PC-2700 and PC3200 Clock speeds of 133 MHz, 166 MHz and 200MHz Supports ECC error detection and correction Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 3 and 4 (clock) Programmable Burst Length (2, 4 or 8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect (SPD) with EEPROM Dual Rank VCC = VCCQ = +2.6V (200MHz) VCC = VCCQ = +2.5V (133 and 166MHz) Gold edge contacts JEDEC standard 200 pin, small-outline, SO-DIMM package * PCB height option: 31.75 mm (1.25")
* This product is under development, is not qualified or characterized and is subject to change or cancellation without notice.
DESCRIPTION
The W3EG264M72EFSU is a 2x64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of eighteen 64Mx8 DDR SDRAMs in FBGA packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option
OPERATING FREQUENCIES
DDR400@CL=3 Clock Speed CL-tRCD-tRP 200MHz 3-3-3 DDR333@CL=2.5 166MHz 2.5-3-3 DDR266@CL=2 133MHz 2-2-2 DDR266@CL=2.5 133MHz 2.5-3-3
September 2004 Rev. 0
1
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PIN CONFIGURATION
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL 51 VSS 101 A9 151 DQ42 1 VREF 2 VREF 52 VSS 102 A8 152 DQ46 53 DQ19 103 VSS 153 DQ43 3 VSS 4 VSS 54 DQ23 104 VSS 154 DQ47 5 DQ0 55 DQ24 105 A7 155 VCC 6 DQ4 56 DQ28 106 A6 156 VCC 7 DQ1 57 VCC 107 A5 157 VCC 8 DQ5 58 VCC 108 A4 158 CK1# 9 VCC 59 DQ25 109 A3 159 VSS 10 VCC 60 DQ29 110 A2 160 CK1 11 DQS0 61 DQS3 111 A1 161 VSS 12 DM0 62 DM3 112 A0 162 VSS 13 DQ2 63 VSS 113 VCC 163 DQ48 14 DQ6 64 VSS 114 VCC 164 DQ52 65 DQ26 115 A10 165 DQ49 15 VSS 16 VSS 66 DQ30 116 BA1 166 DQ53 17 DQ3 67 DQ27 117 BA0 167 VCC 18 DQ7 68 DQ31 118 RAS# 168 VCC 19 DQ8 69 VCC 119 WE# 169 DQS6 20 DQ12 70 VCC 120 CAS# 170 DM6 21 VCC 71 CB0 121 S0# 171 DQ50 22 VCC 72 CB4 122 S1# 172 DQ54 23 DQ9 73 CB1 123 NC 173 VSS 24 DQ13 74 CB5 124 NC 174 VSS 25 DQS1 75 VSS 125 VSS 175 DQ51 26 DM1 76 VSS 126 VSS 176 DQ55 27 VSS 77 DQS8 127 DQ32 177 DQ56 78 DM8 128 DQ36 178 DQ60 28 VSS 29 DQ10 79 CB2 129 DQ33 179 VCC 30 DQ14 80 CB6 130 DQ37 180 VCC 31 DQ11 81 VCC 131 VCC 181 DQ57 32 DQ15 82 VCC 132 VCC 182 DQ61 83 CB3 133 DQS4 183 DQS7 33 VCC 34 VCC 84 CB7 134 DM4 184 DM7 35 CK0 85 NC 135 DQ34 185 VSS 36 VCC 86 DNU 136 DQ38 186 VSS 37 CK0# 87 VSS 137 VSS 187 DQ58 38 VSS 88 VSS 138 VSS 188 DQ62 39 VSS 89 CK2 139 DQ35 189 DQ59 40 VSS 90 VSS 140 DQ39 190 DQ63 41 DQ16 91 CK2# 141 DQ40 191 VCC 42 DQ20 92 VCC 142 DQ44 192 VCC 43 DQ17 93 VCC 143 VCC 193 SDA 44 DQ21 94 VCC 144 VCC 194 SA0 45 VCC 95 CKE1 145 DQ41 195 SCL 46 VCC 96 CKE0 146 DQ45 196 SA1 47 DQS2 97 NC 147 DQS5 197 VCCSPD 48 DM2 98 NC 148 DM5 198 SA2 49 DQ18 99 A12 149 VSS 199 NC 50 DQ22 100 A11 150 VSS 200 VSS
W3EG264M72EFSUXXXD4
ADVANCED
PIN NAMES
Symbol WE#, CAS#, RAS# CK0, CK0# CK1, CK1# CK2, CK2# CKE0-CKE1 S0#-S1# BA0, BA1 A0-A12 SCL SA0-SA2 SDA DM0-DM8 DQS0-DQS8 CB0-CB7 DQ0-DQ63 VREF VCC VSS VCCSPD NC DNU Description Command Input Clock Input Clock Enable Input Chip Select Input Bank Address Address input Serial Clock Presence Detect Address Input Input/Output: Serial PresenceDetect Data Data Write Mask Data Strobe Input/Output: Check Bits Input/Output: Data I/Os, Data bus Supply: SSTL_2 reference voltage Supply: Power Supply: +2.5V 0.2V Supply: Ground Supply: Serial EEPROM Positive Power Supply No Connect Do Not Use
September 2004 Rev. 0
2
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3EG264M72EFSUXXXD4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
S1# S0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS4 DM4 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 BA0, BA1 A0-A12 RAS# CAS# CKE0 CKE1 WE# DM CS# DQS DQ DQ DQ U4 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U13 DQ DQ DQ DQ 120 CK0 CK0# 120 CK1 CK1# 120 CK2 CK2# SPD/EEPROM DDR SDRAMs DDR SDRAMs DDR SDRAMs SA0 SA1 SA2 SCL WP U6, U7, U8, U16, U17, U18 U3, U4, U9, U11, U12, U15 U1, U2, U5, U13, U14, U19 DM CS# DQS DQ DQ DQ U3 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U12 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U2 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U11 DQ DQ DQ DQ DQS8 DM8 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQ DQ DQ DQ U8 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U17 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U1 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U10 DQ DQ DQ DQ DQS7 DM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ U7 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U16 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U0 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U9 DQ DQ DQ DQ DQS6 DM6 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ U6 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U15 DQ DQ DQ DQ DQS5 DM5 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ U5 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U14 DQ DQ DQ DQ
BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs U1-U9 CKE1: DDR SDRAMs U11-U19 WE#: DDR SDRAMs VDD VREF VSS VDDSPD SERIAL PD SDA A0 A1 A2
NOTE: 1. All resistor values are 22 unless otherwise specified.
September 2004 Rev. 0
3
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3EG264M72EFSUXXXD4
ADVANCED
DC ELECTRICAL CHARACTERISTICS
PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) SYMBOL VCC VCCQ VREF VTT VIH VIL VOH VOL MIN 2.3 2.3 0.49 x VCCQ VREF - 0.04 VREF + 0.15 -0.3 -16.8 16.8 MAX 2.7 2.7 0.51 x VCCQ VREF + 0.04 VCC + 0.3 VREF - 0.15 -- -- UNITS V V V V V V mA mA
CAPACITANCE
PARAMETER Input/Output Capacitance: DQ, DQS,DM Input Capacitance: Command and Address Input Capacitance: CK, CK#, Input Capacitance: CKE, S# SYMBOL CI0 CI1 CI2 CI3 MAX 12 47 25 25 UNITS pF pF pF pF
September 2004 Rev. 0
4
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3EG264M72EFSUXXXD4
ADVANCED
IDD SPECIFICATIONS AND CONDITIONS
0C TA +70C; VCC, VCCQ = +2.5V 0.2V DDR400: VCC = VCCQ = +2.6V 0.2V MAX PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle AUTO REFRESH BURST CURRENT: SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands tREFC = tRFC (MIN) SYM IDD0 DDR400 DDR333 DDR266 DDR266 UNITS @CL=3 @CL=2.5 @CL=2 @CL=2.5 2475 2070 2070 1845 mA
IDD1
2745
2340
2340
2115
mA
IDD2P IDD2F
90 990
90 810
90 810
90 720
mA mA
IDD3P IDD3N
810 1080
630 900
630 900
540 810
mA mA
IDD4R IDD4W
2790 2790
2385 2295
2385 2295
2115 2025
mA mA
IDD5 IDD6 IDD7
4185 90 5130
3510 90 4545
3510 90 4545
3330 90 3960
mA mA mA
September 2004 Rev. 0
5
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3EG264M72EFSUXXXD4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
0C TA +70C; VCC = VCCQ = +2.5V 0.2V AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time 403 MIN -0.70 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.60 0.35 0.35 335 MAX +0.70 0.55 0.55 13 13 MIN -0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75 -0.75 0.35 0.35 262 MAX +0.75 0.55 0.55 13 13 MIN -0.75 0.45 0.45 7.5 7.5/10 0.5 0.5 1.75 -0.75 0.35 0.35 265 MAX 0.75 0.55 0.55 13 13 UNITS NOTES ns tCK 26 tCK 26 ns 39, 44 ns 39, 44 ns 39, 44 ns 23, 27 ns 23, 27 ns 27 ns tCK tCK ns 22, 23 tCK tCK tCK ns ns ns ns ns ns
SYMBOL MIN MAX tAC -0.65 +0.65 tCH 0.45 0.55 tCL 0.45 0.55 CL = 3 tCK (3) 5 10 CL = 2.5 tCK (2.5) CL = 2 tCK (2) DQ and DM input hold time relative to DQS tDH 0.40 DQ and DM input setup time relative to DQS tDS 0.40 DQ and DM input pulse width (for each input) tDIPW 1.75 Access window of DQS from CK/CK# tDQSCK -0.55 +0.55 DQS input high pulse width tDQSH 0.35 DQS input low pulse width tDQSL 0.35 DQS-DQ skew, DQS to last DQ valid, per group, per tDQSQ 0.4 access Write command to first DQS latching transition tDQSS 0.72 1.25 DQS falling edge to CK rising - setup time tDSS 0.20 DQS falling edge from CK rising - hold time tDSH 0.20 Half clock period tHP tCH,tCL Data-out high-impedance window from CK/CK# tHZ +0.65 Data-out low-impedance window from CK/CK# tLZ -0.65 +0.65 Address and control input hold time (fast slew rate) tIHF 0.60 Address and control input setup time (fast slew rate) tISF 0.60 Address and control input hold time (slow slew rate) tIHS 0.8
+0.60
+0.75
+0.75
0.4 0.75 1.25 0.20 0.20 tCH,tCL +0.70 -0.70 0.75 0.75 0.8
0.5 0.75 1.25 0.20 0.20 tCH,tCL +0.75 -0.75 0.90 0.90 1
0.5 0.75 1.25 0.2 0.2 tCH, tCL +0.75 -0.75 0.90 0.90 1
30 16, 36 16, 36 12 12 12
September 2004 Rev. 0
6
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3EG264M72EFSUXXXD4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)
0C < TA <+70C; VCC = VCCQ = +2.5V 0.2V AC CHARACTERISTICS RAMETER Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command SYMBOL tISS tIPW tMRD tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR NA tREFC tREFI tVTD tXSNR tXSRD 0 75 200 40 15 55 70 15 15 0.9 0.4 10 0.25 0 0.4 15 1 tQH -tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 MIN 0.8 2.2 12 tHP - tQHS 0.50 70,000 42 18 60 72 18 18 0.9 0.4 12 0.25 0 0.4 15 1 tQH -tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 403 MAX MIN 0.8 2.2 12 tHP - tQHS 0.50 70,000 40 15 60 75 15 15 0.9 0.4 15 0.25 0 0.4 15 1 tQH -tDQSQ 70.3 7.8 0 75 200 ns tCK 0.6 1.1 0.6 335 MAX MIN 1 2.2 15 tHP - tQHS 0.75 120,000 40 20 65 78 20 20 0.9 0.4 15 0.25 0 0.4 15 1 tQH - tDQSQ 70.3 7.8 0.6 1.1 0.6 262 MAX MIN 1 2.2 15 tHP - tQHS 0.75 120,000 265 MAX ns UNITS NOTES 12 ns ns ns ns ns ns ns ns ns ns tCK tCK ns tCK ns tCK ns tCK ns s s ns 22 21 21 18, 19 17 37 37 42 30, 47 22, 23
September 2004 Rev. 0
7
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load:
W3EG264M72EFSUXXXD4
ADVANCED
VTT TT 50 Reference Point 30pF
Output (VOUT (VOUT)
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The mini-mum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with mini-mum cycle time at CL = 2 for -262, and -26A, CL = 2.5 for-335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, TA = 25C, VOUT(DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 12. For slew rates < 1 V/ns and to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -335, slew rates must be 0.5 V/ns. 13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW. 15. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 16. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
17. The intent of the Don't Care state after completion of the postamble is the DQSdriven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above VIH DC (MIN) then it must not transition low (below VIH DC) prior to tDQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute Value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period 64ms. This equates to an aver-age refresh rate of 7.8125s. However, an AUTO REFRESH command must be asserted at least once every 70.3s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyon which functionality is uncertain. Figure 7, Derating Data Valid Window, shows derating curves for duty cycles ranging between 50/50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 26. JEDEC specifies CK and CK# input slew rate must be 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. For -335, slew rates must be 0.5 V/ns. 28. VCC must not vary more than 4 percent if CKE is not active while any bank is active. 29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 30. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 31. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9V, which-ever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either - 300mV or 2.2V, whichever is more positive.
September 2004 Rev. 0
8
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
32. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. c.The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. 33. The voltage levels used are derived from a mini-mum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 34. VIH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 35. VCC and VCCQ must track each other. 36. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
W3EG264M72EFSUXXXD4
ADVANCED
37. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 38. During Initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0.0V, provided a minimum of 42 0 of series resistance is used between the VTT supply and the input pin. 39. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 40. Random addressing changing and 50 percent of data changing at every transfer. 41. Random addressing changing and 100 percent of data changing at every transfer. 42. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 43. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 44. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 45. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 47. The -335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency.
September 2004 Rev. 0
9
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3EG264M72EFSUXXXD4
ADVANCED
ORDERING INFORMATION FOR D4
Part Number W3EG264M72EFSU403D4 W3EG264M72EFSU335D4 W3EG264M72EFSU262D4 W3EG264M72EFSU265D4 Speed 200MHz/400Mbps 166MHz/333Mbps 133MHz/266Mbps 133MHz/266Mbps CAS Latency 3 2.5 2 2.5 tRCD 3 3 2 3 tRP 3 3 2 3 Height* 31.75 (1.25") MAX 31.75 (1.25") MAX 31.75 (1.25") MAX 31.75 (1.25") MAX
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
200-PIN DDR SO-DIMM DIMENSIONS
FRONT VIEW
67.56 (2.66) 3.81 (0.150 ) MAX
2.00 (0.079) R (2X) 31.75 (1.25) 20.00 (0.787) TYP 6.00 (0.236) 2.44 (0.096) 1.10 (0.043) 2.00 (0.079) 0.99 (0.039) TYP 0.46 (0.018) TYP 63.60 (2.504) TYP 0.61 (0.024) TYP
1.80 (0.071) (2X)
PIN 199
PIN 1
BACK VIEW
PIN 200
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
September 2004 Rev. 0 10
PIN 2
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3EG264M72EFSUXXXD4
ADVANCED
PART NUMBERING GUIDE
W 3 E G 264M 72 E F S U xxx D4
WEDC MEMORY DDR GOLD DEPTH (Dual Rank) BUS WIDTH x8 FBGA 2.5V UNBUFFERED SPEED (MHz) PACKAGE 200 PIN
September 2004 Rev. 0
11
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
1GB - 2x64Mx72 DDR SDRAM, UNBUFFERED, FBGA
W3EG264M72EFSUXXXD4
ADVANCED
Revision History Rev #
Rev 0
History
Created
Release Date
9-04
Status
Advanced
September 2004 Rev. 0
12
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

▲Up To Search▲

Price & Availability of W3EG264M72EFSUXXXD4

	To Download W3EG264M72EFSUXXXD4 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .